| Topic | Reading | Recommended Exercises |
|---|---|---|
| Single-Cycle Processors | DDCA 6.1, 7.1-7.3 | Exercises 7.1-7.5, 7.7 |
The reading this week introduces architecture and microarchitecture. We'll be using the MIPS architecture for the remainder of this course.
We will come back to Chapter 6 in more detail later this term, but it's worth reading the introduction to know how the pieces will fit together. Section 6.1 defines the term architecture and explains how it is an abstraction of the hardware. I like to think of the architecture as analogous to an abstract data type.
There are no exercises for this part of the reading. Please make sure to pick up the key definitions (architecture, machine language, assembly language) and a sense of the relationship between those terms and the microarchitecture.
To understand how the single-cycle processor works, we will need to trace the execution of a small number of MIPS assembly instructions (lw, sw, beq, addi, and j). We will learn significantly more about MIPS assembly in the next few weeks, as you will use it in lab, but you may need to do some background reading to get a sense of what these instructions do as you work through the sections in Chapter 7. I recommend using the tables in Appendix B to get a quick sense of what the instructions are intended to do and, if necessary, skimming the related section in Chapter 6 to get a more verbose description of the instructions. Code Examples 6.6 and 6.7 are particularly useful for learning about lw and sw, Code Example 6.12 provides an example of beq, and Code Example 6.14 describes a use of j.
These sections are the focus of this week's material. They explain how the devices we've developed in the first half of the course (registers, shifters, arithmetic logic, etc.) can be assembled into a single-cycle processor that implements MIPS. A single-cycle processor is a computer that completes all of its work -- fetching and decoding an instruction from the user, gathering data from registers, computing, and storing data -- within a single, large cycle. Next week, we'll extend these ideas to build a pipelined processor: one that is far more efficient.
Section 7.1.2 introduces a particularly important idea: the processor is split into a datapath and a control path. Be sure you understand what the purpose of each is and be prepared to identify whether a component is on the datapath or the control path. (As the single-cycle processor is introduced, keep asking yourself, "Is this component in the data or the control path? What, specifically, is it designed to do?") The latter half of section 7.1 contains details about the the processor being built, and you may wish to skip these details until you encounter them in the design in Section 7.3.
Section 7.2 introduces CPI, a measure for evaluating performance of processors. The equation that computes CPI is important, since it demonstrates what we think is important about a processor. You should be familiar with it and prepared to use it (and variants of it).
The majority of the content in this reading is in Section 7.3. The single cycle processor is introduced gradually, through a series of figures. Each figure contains material introduced before in "shadow" and introduces new material in "bold". The first figure in the section, 7.3, is built off of a figure from section 7.1 that introduces the memory components in the processor. Instead of reading the text, I recommend doing a first pass where you just look at the figures. Look at the change in each figure and ask yourself, "What does that wire/component do? Why do we need it?"
After you complete the first two recommended exercises for this week, you should be comfortable tracing the execution of simple operations on the processor. That is, you should know which components of the processor an instruction relies on and how those components implement the function represented by the instruction. In class, we'll build on this by adding new instructions to the processor, as is done in the last few recommended exercises.