| Topic | Reading | Recommended Exercises |
|---|---|---|
| Combinational Logic Timing | DDCA 2.9-2.9.1 | All Exercises 2.32-2.36 (and you can revisit past problems to calculate their delays, too) |
| Synchronous Logic Timing | DDCA 3.5-3.5.3 | All Exercises 3.30-3.32, Question 3.9 |
The reading this week is short but very detailed, and like last week, it takes a lot of practice to get comfortable with the ideas the reading contains. At a high level, the reading describes how to analyze latency: the time required for complete a computation. This concept has a huge impact on computation, since it shows us why computation is not instantaneous.
The first half of the reading focuses on delay within combinational circuits -- propagation and contamination delay using the idea of critical and short paths. The second half adds constraints related to sequential circuits -- hold time and setup time. The italicized terms are very important. Make sure you can define each of them.
Next week, we'll take a step back and will look in depth at a particular type of application: arithmetic circuits. That will let us review the topic of latency while building new circuits.
Section 2.9 introduces propagation and contamination delay. Make sure you have a good definition for both types of delay and are able to compute them for a circuit. Figure 2.69 is particularly important, as it demonstrates the difference between the critical and short paths, which is important to understanding the two types of delay. The examples (2.15 and 2.16) are also very important in this section. You will use them as you solve the assigned exercises.
Section 3.5 extends our understanding of propagation and contamination delay and introduces two constraints that are required in circuits with flip-flops: the hold time and setup time. Make sure you have a good definition of both constraints and know how they are related to propagation and contamination delay. Example 3.9 is the key feature of this section; it puts all of the pieces together to calculate the maximum operating frequency of a circuit.
Don't let the introduction of "clock to Q" before a delay term confuse you: it's still just referring to the propagation or contamination delay for a device. In this case, though, the devices are latches or flip-flops, so we must clarify that the paths are being computed from the point where the clock is introduced (usually, at the gate where the inputs and the clock are combined with an AND) to the output of the latch or flip-flop (Q). The idea is that the inputs to the circuit must arrive before the clock -- otherwise a flip-flop won't register them! -- so we should consider the path as starting from the point where the clock is introduced.
Our text has relatively few examples for sequential timing. We'll do more in class, and you can expect that the quiz could, instead of an exercise, ask for definitions of key terms from this section.